During the process of packaging an integrated circuit, for making the IC chip to be connected with the package pins, the internal IC chip is usually equipped with a core circuit for providing main functions, and input/output pads are located between the core circuit and the external package pins. For designing the output pads and the input pads as the bridge between the core circuit and the external package pins, some additional factors should be taken into consideration because of the special properties thereof. Take an output pad for example. For providing sufficient driving capability, a post driver circuit is necessary for the output pad.
As known, for increasing the operating speed and reducing the power consumption of the core circuit, the core voltage of the core circuit is relatively lower (e.g. 1.8V). In contrary, the output pad connected to the external circuit needs to generate a higher output voltage (e.g. 3.3V).
Generally, the electronic component (e.g. a transistor) of the IC chip is designed to withstand a voltage stress of 1.8V. For withstanding the output voltage (3.3V) at the output pad, the post driver circuit is designed as a two-stage post driver circuit.
FIG. 1A is a schematic circuit diagram illustrating a conventional two-stage post driver circuit. The two-stage post driver circuit 110 is connected between the core circuit 100 and the output pad 120. The core circuit 100 is connected between a first source voltage V1 and a ground terminal GND. For example, the first source voltage V1 is 1.8V. Consequently, a core output signal Ocore outputted from the core circuit 100 is in the range 0V and 1.8V. That is, the high voltage level is 1.8V, and the low voltage level is 0V. The two-stage post driver circuit 110 comprises a control circuit 116, a pull-up unit 112 and a pull-down unit 114. The control circuit 116 is used for receiving the core output signal Ocore, and generating a pull-up controlling signal C_up and a pull-down controlling signal C_down.
The pull-up unit 112 comprises a first P-type transistor P1 and a second P-type transistor P2. The second P-type transistor P2 has a source terminal connected to a second source voltage V2 (e.g. 3.3V), and a gate terminal receiving the pull-up controlling signal C_up. The first P-type transistor P1 has a source terminal connected to a drain terminal of the second P-type transistor P2, a gate connected to the first source voltage V1, and a drain terminal connected to the output pad 120. The pull-down unit 114 comprises a first N-type transistor N1 and a second N-type transistor N2. The second N-type transistor N2 has a source terminal connected to the ground terminal GND, and a gate terminal receiving the pull-down controlling signal C_down. The first N-type transistor N1 has a source terminal connected to a drain terminal of the second N-type transistor N2, a gate terminal connected to the first source voltage V1, and a drain terminal connected to the output pad 120. Moreover, the two-stage post driver circuit 110 is used for generating a pad output signal Opad to the output pad 120. The pad output signal Opad is in the range between 0V and 3.3V. That is, the high voltage level is 3.3V, and the low voltage level is 0V. Moreover, for effectively controlling the second P-type transistor P2 and the second N-type transistor N2, the pull-up controlling signal C_up is in the range between V1 (e.g. 1.8V) and V2 (e.g. 3.3V), and the pull-down controlling signal C_down is in the range between 0V and V1 (e.g. 1.8V).
In a case that the core output signal Ocore is at the high voltage level (1.8V), the pull-up controlling signal C_up from the control circuit 116 is V1 (1.8V), and the pull-down controlling signal C_down from the control circuit 116 is 0V. Consequently, the pull-up unit 112 is turned on, the pull-down unit 114 is turned off, and the high voltage level (3.3V) of the pad output signal Opad is issued to the output pad 120. Whereas, in a case that the core output signal Ocore is at the low voltage level (0V), the pull-up controlling signal C_up from the control circuit 116 is V2 (3.3V), and the pull-down controlling signal C_down from the control circuit 116 is V1 (1.8V). Consequently, the pull-up unit 112 is turned off, the pull-down unit 114 is turned on, and the low voltage level (0V) of the pad output signal Opad is issued to the output pad 120.
Obviously, since each of the transistors P1, P2, N1 and N2 can withstand a voltage stress of 1.8V, the pull-up unit 112 comprises two serially-connected P-type transistors P1 and P2, and the pull-down unit 114 comprises two serially-connected N-type transistors N1 and N2. In a case that the pad output signal Opad is at the low voltage level (0V), the voltage across each P-type transistor is lower than 1.8V. Similarly, in a case that the pad output signal Opad is at the high voltage level (3.3V), the voltage across each N-type transistor is lower than 1.8V.
However, during the level transition of the pad output signal Opad from the two-stage post driver circuit 110, the voltage across the transistor possibly exceeds the voltage stress (1.8V).
FIG. 1B is a plot illustrating the voltage changes at various terminals of the first P-type transistor P1 of the pull-up unit of the conventional two-stage post driver circuit when the pad output signal Opad is changed from a low voltage level (0V) to a high voltage level (3.3V). In a case that the pull-up unit 112 is turned off and the pull-down unit 114 is turned on, the voltage (gp1) at the gate terminal of the first P-type transistor P1 is continuously maintained at the first source voltage V1 (1.8V). Since the drain terminal of the first P-type transistor P1 is connected to the output pad 120, the voltage (dp1) at the drain terminal of the first P-type transistor P1 is 0V. Since the source terminal of the first P-type transistor P1 is in the floating state, the voltage (sp1) at the source terminal of the first P-type transistor P1 is about 1.5V. At the time spot t1, the pull-up unit 112 is turned on and the pull-down unit 114 is turned off. Consequently, the pad output signal Opad is subject to level transition. Meanwhile, the pull-up controlling signal C_up received by the gate terminal of the second P-type transistor P2 has the first source voltage V1 (1.8V), and the voltage (gp1) at the gate terminal of the first P-type transistor P1 is maintained at 1.8V. Consequently, the voltage (dp1) at the drain terminal of the first P-type transistor P1 and the voltage (sp1) at the source terminal of the first P-type transistor P1 are gradually increased to the second source voltage V2 (3.3V).
Please refer to FIG. 1B again. During the level transition of the pad output signal Opad, the voltage (sp1) at the source terminal of the first P-type transistor P1 is increased at a faster speed, but the voltage (dp1) at the drain terminal of the first P-type transistor P1 is increased at a slower speed. Consequently, the difference ΔV between the source voltage (sp1) and the drain voltage (dp1) is greater than 1.8V. Under this circumstance, the first P-type transistor P1 is possibly burned out, and thus the two-stage post driver circuit fails to be normally operated.
Similarly, during the pad output signal Opad is switched from the high voltage level (3.3V) to the low voltage level (0V), the difference between the drain voltage and the source voltage of the first N-type transistor N1 of the pull-down unit 114 may exceed the voltage stress. Under this circumstance, the first N-type transistor N1 is possibly burned out.
As described in FIGS. 1A and 1B, at the moment when the pull-down unit 114 or the pull-up unit 112 of the conventional two-stage post driver circuit 110 is turned on, the difference between the drain voltage and the source voltage of the first N-type transistor N1 or the first P-type transistor P1, which is directly connected to the pad output signal Opad, is usually too large. Consequently, the possibility of damaging the transistor is increased. Therefore, there is a need of providing an improved two-stage post driver circuit to minimize the adverse affect arising from the difference between the drain voltage and the source voltage of the transistor at the moment when the pull-down unit or the pull-up unit is turned on.